The present invention relates to improving the accuracy and efficiency of a phase-locked loop. More specifically, the present invention relates to a method and device for monitoring the frequency discrepancy between two signals in conjunction with at least one data signal so as to improve the accuracy and efficiency of a phase-locked loop.
A phase-locked loop (PLL) is a circuit that is capable of synchronizing an output signal generated by an oscillator with a reference or input signal in frequency as well as in phase. FIG. 1 shows a simplified block diagram of the functional elements of a conventional PLL. A conventional PLL generally includes a voltage-controlled oscillator (VCO) 10, a phase detector 12, and a loop filter 14. A PLL uses feedback to maintain an output signal in a specific phase with a reference signal. The VCO 10 generally oscillates at an angular frequency which is determined by the output signal 20 of the loop filter 14 which, in turn, is controlled by the output signal 18 of the phase detector 12. In turn, the output 22 of the VCO 10 and the external reference or input signal 16 dictate the output signal 18 of the phase detector 12. Hence, if the phase error between the VCO output 22 and the external reference or input signal 16 is not zero or within a tolerable margin, the phase detector 12 will develop a nonzero output 18, thereby via the loop filter 14 causing the VCO 10 to produce an output signal 22 that is synchronized or locked with the external reference or input signal 16 and reducing the phase error to an acceptable level.
The process of achieving a lock between the VCO output 22 and the external reference or input signal 16 involves two steps. First, the frequencies of the two signals 16, 22 have to be matched. When the two frequencies are matched, the two signals 16, 22 are sometimes referred to as being in a frequency-locked mode. Once the frequency-locked mode is achieved, the phases of the two signals 16, 22 are then matched thereby achieving a phase-locked mode. In other words, the frequency-locked mode is a prerequisite to achieving the phase-locked mode. Once the phase-locked mode is achieved, the PLL can then perform its intended functions.
PLLs are used in many applications including frequency synthesis, modulation, demodulation, and data and clock recovery. For example, in digital communications, it is frequently necessary to extract a coherent clock signal from an input data stream. A PLL is often used for this task by locking a VCO output to the input data stream. Once locked, the VCO output is essentially the clock signal of the input data stream and thus can then be used to extract the data bits from the input data stream.
Quite often, however, two signals for a variety of reasons may disengage from the phase-locked mode. This can happen when the two signals are no longer in frequency-locked mode. For example, when a data signal becomes jittery or disappears entirely, the frequencies of the data signal and the VCO signal can no longer match, thereby causing the two signals to disengage from the frequency-locked mode and subsequently from the phase-locked mode. Therefore, it would be desirable to provide a method and device that is capable of reliably detecting whether two signals are in frequency-locked mode thereby ensuring that the phase-locked mode is maintained.
In addition, different systems often require different degrees of precision 25 to achieve a frequency-locked mode depending on the purposes of the systems. Some systems may require two signals to be closely matched before a frequency-locked mode is considered achieved, while others may permit a wider margin of matching. Therefore, it would be desirable to provide a method and device that is capable of having an adjustable threshold for determining whether a frequency-locked mode is achieved.
Further, as mentioned above, before a PLL can perform its intended functions, it must be engaged in a phase-locked mode first which, in turn, requires as a prerequisite a frequency-locked mode to be achieved. Conversely, a phase-locked mode is disengaged when the prerequisite frequency-locked mode is no longer present. Any unnecessary or mistaken disengagement of the frequency-locked mode thus disrupts the phase-locked mode and consequently prevents the PLL from performing its intended functions. Therefore, it would be desirable to provide a method and device that is capable of efficiently monitoring the activation of the frequency-locked mode so as to optimize the continued operation of a PLL.
Moreover, very often when a PLL is engaged in a phase-locked mode and no data is available for detection, the VCO signal tends to drift and eventually will no longer be considered to be in frequency-locked mode with the external reference or input signal. During this period when the frequency-locked mode is lost, a PLL is not capable of detecting incoming data and such data are thus lost. When this occurs, the phase-locked mode has to be disengaged so as to allow the frequency-locked mode to be re established so that as soon as data is available, the PLL can switch to the phase-locked mode to capture the data. Therefore, it would be desirable to provide a method and device that is capable of efficiently monitoring and controlling the transition between the phase-locked mode and the frequency-locked mode so as to minimize data loss. The present invention satisfies the above as well as other needs.